Chapter 1: State of the Art Programmable Logic 1
Chapter 2: Vivado Design Tools 17
Chapter 3: IP Flows 23
Chapter 4: Gigabit Transceivers 35
Chapter 5: Memory Controllers 49
Chapter 6: Processor Options 65
Chapter 7: Vivado IP Integrator 75
Chapter 8: SysGen for DSP 85
Chapter 9: Synthesis 97
Chapter 10: C Based Design 111
Chapter 11: Simulation 127
Chapter 12: Clocking 141
Chapter 13: Stacked Silicon Interconnect (SSI) 155
Chapter 14: Timing Closure 167
Chapter 15: Power Analysis and Optimization 179
Chapter 16: System Monitor 191
Chapter 17: Hardware Debug 205
Chapter 18: Emulation Using FPGAs 221
Chapter 19: Partial Reconfiguration & Hierarchical Design 239