Verilog® Quickstart

Welcome to the world of Verilog! Once you read this book, you will join the ranks of the many successful engineers who use Verilog. I have been using Verilog since 1986 and teaching Verilog since 1987. I have seen many different Verilog courses and many approaches to learning Verilog. This book generally follows the outline of the Verilog class that I teach at the University of California, Santa Cruz, Extension. This book does not take a "cookie-cutter" approach to learning Verilog, nor is it a completely theoretical book. Instead, what we will do is go through some of the formal Verilog syntax and definitions, and then show practical uses. Once we cover most of the constructs of the language, we will look at how style affects the constructs you choose while modeling your design. This is not a complete and exhaustive reference on Verilog. If you want a Verilog reference, I suggest one of the Open Verilog International (OVI) reference manuals.

List of Figures. List of Examples. List of Tables. 1. Introduction. 2. Introduction to the VERILOG Language. 3. Structural Modeling. 4. Behavioral Modeling. 5. Operators. 6. Working with Behavioral Modeling. 7. User-Defined Primitives. 8. Parameterized Modules. 9. State Machines. 10. Modeling Tips. 11. Modeling Style Trade-offs. 12. Test Benches and Test Management. 13. Common Errors. 14. Debugging a Design. Appendix A: Gate Level Details. Appendix B: Example Summary. Index.