VLSI Algorithms and Architectures Aegean Workshop on Computing, Loutraki, Greece, July 8-11, 1986. Proceedings

Digital filtering in VLSI.- Two processor scheduling is in NC.- Breaking symmetry in synchronous networks.- Parallel ear decomposition search (EDS) and st-numbering in graphs.- A unifying framework for systolic designs.- Optimal tradeoffs for addition on systolic arrays.- On the connection between hexagonal and unidirectional rectangular systolic arrays.- Lower bounds for sorting on mesh-connected architectures.- Diogenes, circa 1986 ????? ??? ??? ????o ????o?o.- Nonsequential computation and laws of nature.- Linear algorithms for two CMOS layout problems.- Some new results on a restricted channel routing problem.- Efficient modular design of TSC checkers for m-out-of-2m codes.- Vlsi algorithms and pipelined architectures for solving structured linear system.- A high-performance single-chip vlsi signal processor architecture.- Exploiting hierarchy in VLSI design.- A polynomial algorithm for recognizing images of polyhedra.- Parallel tree techniques and code optimization.- AT2-optimal galois field multiplier for VLSI.- Linear and book embeddings of graphs.- Efficient parallel evaluation of straight-line code and arithmetic circuits.- A logarithmic boolean time algorithm for parallel polynomial division.- A polynomial algorithm for recognizing small cutwidth in hypergraphs.- A generalized topological sorting problem.- Combinational static CMOS networks.- Fast and efficient parallel linear programming and linear least squares computations.- On the time required to sum n semigroup elements on a parallel machine with simultaneous writes.- A comparative study of concurrency control methods in B-trees.- Generalized river routing — Algorithms and performance bounds.