Neuro-inspired Computing Using Resistive Synaptic Devices

This book summarizes the recent breakthroughs in hardware implementation of neuro-inspired computing using resistive synaptic devices. The authors describe how two-terminal solid-state resistive memories can emulate synaptic weights in a neural network. Readers will benefit from state-of-the-art summaries of resistive synaptic devices, from the individual cell characteristics to the large-scale array integration. This book also discusses peripheral neuron circuits design challenges and design strategies. Finally, the authors describe the impact of device non-ideal properties (e.g. noise, variation, yield) and their impact on the learning performance at the system-level, using a device-algorithm co-design methodology.

Chapter1: Introduction to Neuro-Inspired Computing using Resistive Synaptic Devices.- Part I: Device-level Demonstrations of Resistive Synaptic Devices.- Chapter2: Phase Change Memory based Synaptic Devices.- Chapter3: Pr0.7Ca0.3MnO3 (PCMO) based Synaptic Devices.- Chapter4: TaOx/TiO2 based Synaptic Devices.- Part II: Array-level Demonstrations of Resistive Synaptic Devices and Neural Networks.- Chapter5: Training and Inference in Hopfield Network using 10×10 Phase Change Synaptic Array.- Chapter6: Experimental Demonstration of Firing-Rate Neural Networks based on Metal-Oxide Memristive Crossbars.- Chapter7: Weight Tuning of Resistive Synaptic Devices and Convolution Kernel Operation on 12×12 Cross-Point Array.- Chapter8: Spiking Neural Network with 256×256 PCM Array.- Part III: Circuit, Architecture and Algorithm-level Design of Resistive Synaptic Devices based Neuromorphic System.- Chapter9: Peripheral Circuit Design Considerations of Neuro-inspired Architectures.- Chapter10: Processing-in-Memory Architecture Design for Accelerating Neuro-Inspired Algorithms.- Chapter11: Multi-layer Perceptron Algorithm: Impact of Non-Ideal Conductance and Area-Efficient Peripheral Circuits.- Chapter12: Impact of Non-Ideal Resistive Synaptic Device Behaviors on Implementation of Sparse Coding Algorithm.- Chapter13: Binary OxRAM/CBRAM Memories for Efficient Implementations of Embedded Neuromorphic Circuits.