Electronic Devices Architectures for the NANO-CMOS Era

In-depth and timely, this examination gives a state-of-the-art overview by internationally-recognized researchers of the electronic device architectures required for the NanoCMOS era and beyond. Challenges relevant to the scaling of CMOS Nanoelectronics are addressed through the different Core CMOS and Memory Devices options in the first part of the book. The second part reviews the New device Concepts for Nanoelectronics Beyond CMOS. What are the fundamental limits of core CMOS, and can we improve the scaling by the introduction of new materials or processes? Will the new architectures using SOI, multigates, or multichannels improve the trade-off between performance and power consumption and relax the constraints of new material integration? Can quantum computing replace binary-based protocols to enhance the information processing power? These questions and others are answered in this book.

In this book, internationally recognized researchers give a state-of-the-art overview of the electronic device architectures required for the nano-CMOS era and beyond. The book covers the fundamental limits of core CMOS, improving scaling by the introduction of new materials or processes, multigates and multichannels, and quantum computing.

CMOS Nanoelectronics. Reaching the End of the RoadmapCore CMOSPhysical and Technological Limitations of NanoCMOS Devices to the End of the Roadmap and Beyond, S Deleonibus, O Faynot, B de Salvo, T Ernst, C Le Royer, T Poiroux & M VinetAdvanced CMOS Devices on Bulk and SOI: Physics, Modeling and Characterization, T Poiroux & G Le CarvalDevices Structures and Carrier Transport Properties of Advanced CMOS using High Mobility Channels, S Takagi, T Tezuka, T Irisawa, S Nakaharai, T Numata, K Usuda, N Sugiyama, M Shichijo, R Nakane & S SugaharaHigh-kappa Gate Dielectrics, H Wong, K Shiraishi, K Kakushima & H IwaiFabrication of Source and Drain — Ultra Shallow Junction, B MizunoNew Interconnect Schemes: End of Copper, Optical Interconnects? S Laval, L Vivien, E Cassan, D Marris-Morini & J-M FédéliMemory DevicesTechnologies and Key Design Issues for Memory Devices, K Kim & G JeongFeRAM and MRAM Technologies, Y ArimotoAdvanced Charge Storage Memories: From Silicon Nanocrystals to Molecular Devices, B De Salvo & G MolasNew Concepts for Nanoelectronics. New Paths Added to CMOS Beyond the End of the RoadmapSingle Electron Devices and Applications, J Gautier, X Jehl & M SanquerElectronic Properties of Organic Monolayers and Molecular Devices, D VuillaumeCarbon Nanotube Electronics, V Derycke, A Filoramo & J-P BourgoinSpin Electronics, K-J Lee & S H LimThe Longer Term: Quantum Information Processing and Communication, P Jorrand

Simon Deleonibus (MSc 1979, PhD 1982, Paris University) was with Thomson Semiconducteurs, Grenoble, France, from 1981 to 1986 in device engineering development and then production. In 1986 he was with CEA LETI advanced device and process modules research specialising in CMOS and flash memories applications. From 1998 to 2008 he was the director of the Electronic Nanodevices Laboratory with 55 researchers under his charge. Since 2008, he is the chief scientific director of Silicon Technologies of LETI. He owns the initial patent on contact plug principle, widely used as a standard process by the semiconductor industry. He actualised the first 20-nm gate length MOSFET, the world’s smallest transistor, in June 1999. He is the editor of IEEE Transactions on Electron Devices and a member of the International Technology Roadmap of Semiconductors (ITRS), of the board of directors of the Nanosciences Foundation and of The European Research Council Engineering Panel. A Fellow of the IEEE, he is its distinguished lecturer. He is also the research director of the French CEA.