Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differencesbetween asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example

Introduction to Asynchronous Logic.- Overview of NULL Convention Logic (NCL).- Combinational NCL Circuit Design.- Sequential NCL Circuit Design.- NCL Throughput Optimization.- Low-Power NCL Design.- Comprehensive NCL Design Example.

Scott C. Smith received B.S. degrees in Electrical Engineering and Computer Engineering and an M.S.E.E., with emphasis in Computers and Digital Systems, from the University of Missouri, Columbia in 1996 and 1998, respectively, and a Ph.D. in Computer Engineering, with an emphasis in Computer Architecture and Digital Systems, from the University of Central Florida in 2001. He started as an Assistant Professor in the Electrical and Computer Engineering department at University of Missouri, Rolla in 2001, was promoted to Associate Professor and tenured in 2007, and is currently at the University of Arkansas as a Tenured Associate Professor in the Department of Electrical Engineering, an Adjunct Associate Professor in the Department of Computer Science & Computer Engineering, and Director of the Asynchronous Digital Design (ADD) Laboratory. Dr. Smith is an expert in asynchronous digital design, specifically focusing on NULL Convention Logic (NCL). He wrote his Ph.D. dissertation on design and optimization of NCL circuits, and has authored numerous publications on asynchronous logic. Dr. Smith is the recipient of a Phase I NSF Course Curriculum and Laboratory Improvement (CCLI) Grant to develop educational modules for incorporating asynchronous design and testing into the undergraduate Computer Engineering curriculum, and Phase II CCLI grant, along with Dr. Jia Di, to significantly expand the developed curricular content and broadly disseminate it to universities and colleges throughout the nation. The developed materials include lecture notes, example problems, group projects, and asynchronous digital design libraries, consisting of a VHDL library of asynchronous gates, components, and functions, and transistor-level and physical-level libraries of fundamental asynchronous gates, which can be downloaded from the project website. Dr. Smith's research interests include CAD Tool Development for Asynchronous Circuits, Asynchronous FPGA Design, VHDL, VLSI, Computer Architecture, Embedded System Design, Evolvable Hardware, Secure/Trustable Hardware, and Wireless Sensor Networks.