Design and Applications of Emerging Computer Systems

This book provides a single-source reference to the state-of-the-art in emerging computer systems. The authors address the technological contributions and developments at various hardware levels of new systems that compute under novel operational paradigms such as stochastic, probabilistic/inexact, neuromorphic, spintronic, bio-inspired and in-memory computing. Coverage includes the entire stack, i.e., from circuit, architecture, up to system level. This book includes tutorials, reviews and surveys of current theoretical/experimental results, design methodologies and a range of applications.

Part-I. In-Memory Computing, Neuromorphic Computing and Machine Learning.- Chapter 1. Emerging Technologies for Memory-Centric Computing.- Chapter 2. An overview of Computation-in-Memory (CIM) architectures.- Chapter 3. Towards Spintronics Non-Volatile Computing-in-Memory Architecture.- Chapter 4. Is Neuromorphic Computing the Key to Power-Efficient Neural Networks?: A Survey.- Chapter 5. Emerging Machine Learning using Siamese and Triplet Neural Networks.- Chapter 6. An active storage system for intelligent data analysis and management.- Chapter 7. Error-Tolerant Techniques for Classifiers beyond Neural Networks for Dependable Machine Learning.- Part-II. Stochastic Computing.- Chapter 8. Efficient Random Number Source Designs Based on D Flip-Flops for Stochastic Computing.- Chapter 9. Stochastic multipliers from serial to parallel.- Chapter 10. Ising Models Based On Stochastic Computing.- Chapter 11. Stochastic and Approximate Computing for Deep Learning: A Survey.- Chapter 12. Stochastic Computing and Morphological Neural Networks: an ultra-high energy-efficient Machine Learning methodology.- Chapter 13. Characterizing Stochastic Number Generators for Accurate Stochastic Computing.- Part-III. Inexact/Approximate Computing.- Chapter 14. Automated Generation and Evaluation of Application-Oriented Approximate Arithmetic Circuits.- Chapter 15. Automatic Approximation of Computer Systems through Multi-Objective Optimization.- Chapter 16. Evaluation of the functional impact of approximate arithmetic circuits on two application examples.- Chapter 17. Energy Efficient Approximate Floating-Point FFT Design Using A Top-Down Methodology.- Chapter 18. Approximate Computing in Machine Learning Systems: Cross-level designs and methodologies.- Chapter 19. Adaptive Approximate Accelerators with Controlled Quality using Machine Learning.- Chapter 20. Design Wireless Communication Circuits and Systems Using Approximate Computing.- Chapter 21. Low-cost Logarithmic Floating-point Multipliers for Efficient Neural Network Training.- Part-IV. Quantum Computing and Other Emerging Computing.- Chapter 22. Cryogenic CMOS for quantum computing.- Chapter 23. Memristive Crossbar System towards Hardware Accelaration of Quantum Algorithms.- Chapter 24. A Review of Posit Arithmetic for Energy Efficient Computation: Methodologies, Applications, and Challenges.- Chapter 25. Designing Fault Tolerant Digital circuits in Quantum-dot Cellular Automata.- Chapter 26. CMOS Circuit-based Fully Connected Ising Machines with Parallel Updating and Its Applications in MIMO Detection .- Chapter 27. Approximate Communication in Network-on Chips for Training and Inference of Image Classification Models.

Weiqiang Liu is currently a Professor and the Vice Dean of College of Electronic and Information Engineering & College of Integrated Circuits, Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China. He received the B.Sc. degree in Information Engineering from NUAA and the Ph.D. degree in Electronic Engineering from Queen's University Belfast (QUB), Belfast, United Kingdom, in 2006 and 2012, respectively. In Dec. 2013, he joined the College of Electronic and Information Engineering, NUAA, where he is now a full professor.

 His research interest mainly focuses on energy efficient and secure computing integrated circuits and systems that include approximate computing, computer arithmetic, hardware security, VLSI design for DSP and cryptography, and mixed-signal integrated circuits. His research has been funded by Natural Science Foundation China (NSFC), State Grid Corporation of China, et al. He has published 2 research books by Springerand Artech House, over 200 leading journal and conference papers (over 80 IEEE and ACM journals including 8 invited papers such as Proceedings of the IEEE). His papers were selected as the Highlight Paper of IEEE TCAS-I in the 2021 January Issue, the two Feature Papers of IEEE CASM in the 2021 4th issue and IEEE TC in the 2017 December issue, IET CDT Editor's Choice Award in 2021, Best Paper Candidates of ISCAS 2011, GLSVLSI 2015 and GLSVLSI 2022. He received the prestigious Excellent Young Scientists Fund from NSFC in 2020 and the Young Scientist Award by Fok Ying Tung Education Foundation, Ministry of Education, China, 2022. He has been listed in the Stanford University's list of the top 2% scientists in the world. 

He is the Vice President-Elect for TA of the IEEE Nanotechnology Council (NTC). He has served as a Steering Committee Chair of IEEE Transactions on VLSI Systems, Associate Editors of IEEE Transactions on Circuits and Systems I: Regular Paper, IEEE Transactions on Emerging Topic in Computing and Computers, IEEE Transactions on Computers, IEEE Open Journal of Computer Society and IET Computers & Digital Techniques, a Guest Editor of Proceedings of the IEEE and IEEE Nanotechnology Magazine, the member of IEEE Symposium on Computer Arithmetic (ARITH) Steering Committee Member, 2020 TETC and AsianHOST 2021 Best Paper Award Committee. He is the Program Co-Chair of IEEE ARITH 2020, 17th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2022) and IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2023), and program members for a number of international conferences including DAC, ARITH, DATE, ASP-DAC, ISCAS, ASAP, ISVLSI, ICCD, GLSVLSI, AsianHOST, NANORACH, AICAS, SiPS, NMDC et al. He is a tutorial organizer and speaker in DAC 2022, DATE 2022, IEEE ISCAS 2021 and COINS 2021. He is a member of both Circuits & Systems for Communications (CASCOM) Technical Committee and VLSI Systemsand Applications (VSA) Technical Committee, IEEE Circuits and Systems Society. He is a Senior Member of the IEEE, CIE and CCF.

Dr. Jie Han received the B.Sc. degree in electronic engineering from Tsinghua University, Beijing, China, in 1999 and the Ph.D. degree from the Delft University of Technology, The Netherlands, in 2004. He is currently a Professor and Director of Computer Engineering in the Department of Electrical and Computer Engineering at the University of Alberta. His research interests include approximate computing, stochastic computing, brain-inspired learning systems and neural networks, reliability and fault tolerance, nanoelectronic circuits and systems, novel computational models for learning and biological applications.

Dr. Han was a recipient of the Best Paper Awards at the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2015) and the Automation and Test in Europe Conference (DATE 2023), as well as four Best Paper Nominations at the 25th IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI 2015), NANOARCH 2016, the 19th International Symposium on Quality Electronic Design (ISQED 2018) and DATE 2022. He was nominated for the 2006 Christiaan Huygens Prize of Science by the Royal Dutch Academy of Science (Koninklijke Nederlandse Akademie van Wetenschappen (KNAW) Christiaan Huygens Wetenschapsprijs). His work was recognized by the 125th anniversary issue of the Science Magazine, for developing a theory of fault-tolerant nanocircuits (2003).

Dr. Han serves (or served) as an Associate Editor for the IEEE Transactions on Emerging Topics in Computing (TETC), IEEE Transactions on Nanotechnology, IEEE Circuits and Systems Magazine (CASM), IEEE Open Journal of the Computer Society, Microelectronics Reliability and the Journal of Electronic Testing: Test and Application (JETTA, Elsevier).

He served as a General Chair for the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH