Assessing Fault Model and Test Quality

For many years, the dominant fault model in automatic test pattern gen­ eration (ATPG) for digital integrated circuits has been the stuck-at fault model. The static nature of stuck-at fault testing when compared to the extremely dynamic nature of integrated circuit (IC) technology has caused many to question whether or not stuck-at fault based testing is still viable. Attempts at answering this question have not been wholly satisfying due to a lack of true quantification, statistical significance, and/or high computational expense. In this monograph we introduce a methodology to address the ques­ tion in a manner which circumvents the drawbacks of previous approaches. The method is based on symbolic Boolean functional analyses using Or­ dered Binary Decision Diagrams (OBDDs). OBDDs have been conjectured to be an attractive representation form for Boolean functions, although cases ex­ ist for which their complexity is guaranteed to grow exponentially with input cardinality. Classes of Boolean functions which exploit the efficiencies inherent in OBDDs to a very great extent are examined in Chapter 7. Exact equa­ tions giving their OBDD sizes are derived, whereas until very recently only size bounds have been available. These size equations suggest that straight­ forward applications of OBDDs to design and test related problems may not prove as fruitful as was once thought.

1. Introduction.- 1.1 Functional Test Generation Techniques.- 1.2 Representing Symmetric Functions with OBDDs.- 1.3 Controllability, Observability, and Detectability.- 1.4 Modeling ATPG and Measuring Test Quality.- 2. Fault Modeling.- 2.1 Fault Model Assumptions.- 2.2 Fault Model Classes.- 3. Ordered Binary Decision Diagrams.- 3.1 History of OBDDs.- 3.2 Properties of OBDDs.- 3.3 Shannon’s Expansion Theorem.- 4. Automatic Test Pattern Generation.- 4.1 ATPG Problem Specification.- 4.2 Conventional ATPG Algorithms.- 4.3 Boolean Functional Test Generation.- 5. Defect Level.- 5.1 Definition of Defect Level.- 5.2 Defect Level Simplifying Assumptions.- 5.3 Defect Level Models.- 6. Test Performance Evaluation.- 6.1 Theoretical Approaches.- 6.2 Fault Simulation Approaches.- 6.3 Test Application Approaches.- 6.4 Layout Driven Approaches.- 7. OBDDs for Symmetric Functions.- 7.1 Symmetric Functions.- 7.2 Circuit and Function Terminology.- 7.3 The Symmetry Diagram.- 7.4 Removing Redundant Vertices.- 7.5 Derivation of OBDD Size Equations.- 7.6 Uniqueness Argument.- 7.7 OBDDs for Tree Circuits.- 7.8 OBDD Size Summary.- 8. Difference Propagation.- 8.1 The Development of Difference Propagation.- 8.2 Deriving the Input-Output Relationships.- 8.3 The Difference Propagation Algorithm.- 8.4 The Efficiency of Differences.- 8.5 Using Functional Decomposition.- 9. Fault Model Behavior.- 9.1 Selection of Fault Models and Fault Sets.- 9.2 Fault Behavior Results and Analysis.- 10.The Contributions of Con/Obs to Test.- 10.1 Motivation to Study Con/Obs.- 10.2 Definitions of Con/Obs.- 10.3 Generating Con/Obs Information.- 10.4 Con/Obs Results and Analysis.- 10.5 Con/Obs Summary.- 11.Analyzing Test Performance.- 11.1 Defect Level Motivation.- 11.2 ATPG Model Development.- 11.3 Fault SetSelectability.- 11.4 Probabilistic Non-Target Defect Coverage.- 11.5 Faults Sets.- 11.6 Test Performance Results.- 11.7 Implications to Defect Level.- 12. Conclusions.- 13.Suggestions for Future Research.- 13.1 Extensions to OBDD Size Research.- 13.2 Extensions to Difference Propagation.- 13.3 Extensions to Test Quality Research.- 13.4 Using Ordered Partial Decision Diagrams.- 13.5 General Extensions.