Advances in Electronic Testing Challenges and Methodologies

Advances in Electronic Testing: Challenges and Methodologies is a new type of edited volume in the Frontiers in Electronic Testing book series devoted to recent advances in electronic circuits testing. The book is a comprehensive elaboration on important topics which capture major research and development efforts today. The motivation and inspiration behind this book is to deliver a thorough text that focuses on the evolution of test technology, provides insight about the abiding importance of discussed topics, records today’s state of the art and industrial practices and trends, reveals the challenges for emerging testing methodologies, and envisages the future of this journey.

The book consists of eleven edited chapters written by experts in Defect-Oriented Testing, Nanometer Technologies Failures and Testing, Silicon Debug, Delay Testing, High-Speed Test Interfaces, DFT-Oriented Low-Cost Testers, Embedded Cores and System-on-Chip Testing, Memory Testing, Mixed-Signal Testing, RF Testing and Loaded Board Testing. Contributing authors are affiliated with (in alphabetical order) Agilent, ARM, Balearic Islands Univ., IBM, Inovys, Intel, LogicVision, Magma, Mentor Graphics, New Mexico Univ., Sandia National Labs, Synopsys, Teradyne and Texas Instruments.

Advances in Electronic Testing: Challenges and Methodologies is an advanced textbook and reference point for senior undergraduate and graduate students in MSc or PhD tracks, professors and research leaders in the electronic testing domain. It is also for industry design and test engineers and managers seeking a global view and understanding of test technology practices and methodologies and a dense elaboration on test-related issues they face in their development projects.

"There is a definite need for documenting the advances in testing … I find the work of this edited volume by Dimitris Gizopoulos and his team of authors to be significant and timely. […] the book provides, besides novel test methodologies, a collective insight into the emerging aspects of testing. This, I think, is beneficial to practicing engineers and researchers both of whom must stay at the forefront of technology. […] This latest addition to the Frontiers Series is destined to serve an important role." From the Foreword by Vishwani D. Agrawal, Consulting Editor, Frontiers in Electronic Testing Book Series.

Foreword by Vishwani D. Agrawal Preface by Dimitris Gizopoulos Contributing Authors Dedication Chapter 1—Defect-Oriented Testing by Robert C. Aitken 1.1 History of Defect-Oriented Testing 1.2 Classic Defect Mechanisms 1.3 Defect Mechanisms in Advanced Technologies 1.4 Defects and Faults 1.5 Defect-Oriented Test Types 1.6 Experimental Results 1.7 Future Trends and Conclusions Acknowledgments References Chapter 2—Failure Mechanisms and Testing in Nanometer Technologies by Jaume Segura, Charles Hawkins and Jerry Soden 2.1 Scaling CMOS Technology 2.2 Failure Modes in Nanometer Technologies 2.3 Test Methods for Nanometer ICs 2.4 Conclusion References Chapter 3—Silicon Debug by Doug Josephson and Bob Gottlieb 3.1 Introduction 3.2 Silicon Debug History 3.3 Silicon Debug Process 3.4 Debug Flow 3.5 Circuit Failures 3.6 A Case Study in Silicon Debug 3.7 Future Challenges for Silicon Debug 3.8 Conclusion Acknowledgements References Chapter 4—Delay Testing by Adam Cron 4.1 Introduction 4.2 Delay Test Basics 4.3 Test Application 4.4 Delay Test Details 4.5 Vector Generation 4.6 Chip Design Constructs 4.7 ATE Requirements 4.8 Conclusions: Tests vs. Defects Acknowledgements References Chapter 5—High-Speed Digital Test Interfaces by Wolfgang Maichen 5.1 New Concepts 5.2 Technology and Design Techniques 5.3 Characterization and Modeling 5.4 Outlook References Chapter 6—DFT-Oriented, Low-Cost Testers by Al Crouch and GeirEide 6.1 Introduction 6.2 Test Cost – the Chicken and the Low Cost Tester 6.3 Tester Use Models 6.4 Why and When is DFT Low Cost? 6.5 What does Low Cost have to do with the Tester? 6.6 Life, the Universe, and Everything References Recommended Reading Chapter 7—Embedded Cores and System-on-Chip Testing by Rubin Parekhji 7.1 Embedded Cores and SOCs 7.2 Design and Test Paradigm with Cores and SOCs 7.3 DFT for Embedded Cores and SOCs 7.4 Test Access Mechanisms 7.5 ATPG for Embedded Cores and SOCs 7.6 SOC Test Modes 7.7 Design for At-speed Testing 7.8 Design for Memory and Logic BIST 7.9 Conclusion Acknowledgements References Chapter 8—Embedded Memory Testing by R. Dean Adams 8.1 Introduction 8.2 The Memory Design Under Test 8.3 Memory Faults 8.4 Memory Test Patterns 8.5 Self Test 8.6 Advanced Memories & Technologies 8.7 Conclusions References Chapter 9—Mixed-Signal Testing and DfT by Stephen Sunter 9.1 A Brief History 9.2 The State of the Art 9.3 Advances in the Last 10 Years 9.4 Emerging Techniques and Directions 9.5 EDA Tools for Mixed-Signal Testing 9.6 Future Directions References Chapter 10—RF Testing by Randy Wolf, Mustapha Slamani, John Ferrario and Jayendra Bhagat 10.1 Introduction 10.2 Testing RF ICs 10.3 RF Test Cost Reduction Factors 10.4 Test Hardware 10.5 Hardware Development Process 10.6 High Frequency Simulation Tools 10.7 Device Under Test Interface 10.8 Conclusions Acknowledgements References Chapter 11—Loaded