Strain-Engineered MOSFETs

NOTE EDITORE

Currently strain engineering is the main technique used to enhance the performance of advanced silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Written from an engineering application standpoint, Strain-Engineered MOSFETs introduces promising strain techniques to fabricate strain-engineered MOSFETs and to methods to assess the applications of these techniques. The book provides the background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOSFETs at nanoscale. This book focuses on recent developments in strain-engineered MOSFETS implemented in high-mobility substrates such as, Ge, SiGe, strained-Si, ultrathin germanium-on-insulator platforms, combined with high-k insulators and metal-gate. It covers the materials aspects, principles, and design of advanced devices, fabrication, and applications. It also presents a full technology computer aided design (TCAD) methodology for strain-engineering in Si-CMOS technology involving data flow from process simulation to process variability simulation via device simulation and generation of SPICE process compact models for manufacturing for yield optimization. Microelectronics fabrication is facing serious challenges due to the introduction of new materials in manufacturing and fundamental limitations of nanoscale devices that result in increasing unpredictability in the characteristics of the devices. The down scaling of CMOS technologies has brought about the increased variability of key parameters affecting the performance of integrated circuits. This book provides a single text that combines coverage of the strain-engineered MOSFETS and their modeling using TCAD, making it a tool for process technology development and the design of strain-engineered MOSFETs.

SOMMARIO

IntroductionTechnology ScalingSubstrate-Induced Strain EngineeringProcess-Induced Stress EngineeringElectronic Properties of Strained SemiconductorsStrain-Engineered MOSFETsNoise in Strain-Engineered DevicesTechnology CAD of Strain-Engineered MOSFETsReliability of Strain-Engineered MOSFETsProcess Compact ModellingProcess-Aware DesignSummaryAdditional ReadingSubstrate-Induced Strain Engineering in CMOS TechnologySubstrate EngineeringStrained SiGe Film GrowthStrained SiGe:C Film GrowthStrained Si Films on Relaxed Si1–xGexStrained Si on SOIStrained Ge Film GrowthStrained Ge MOSFETsHeterostructure SiGe/SiGe:C Channel MOSFETsStrained Si MOSFETsHybrid Orientation TechnologySummaryReview QuestionsReferencesProcess-Induced Stress Engineering in CMOS TechnologyStress EngineeringSi1–xGex in Source/DrainSi1–yCy in Source/DrainShallow Trench Isolation (STI)Contact Etch Stop Layer (CESL)SilicidationStress Memorisation Technique (SMT)Global vs. Local StrainBEOL Stress: Through-Silicon ViaTSV ModellingSummaryReview QuestionsReferencesElectronic Properties of Strain-Engineered SemiconductorsBasics of Stress EngineeringStress–Strain RelationshipsStrain-Engineered MOSFETs: CurrentEnergy Gap and Band StructureSilicon Conduction BandSilicon Valence BandBand Structure under StressPiezoresistive Mobility ModelStrain-Induced Mobility ModelImplementation of Mobility ModelSummaryReview QuestionsReferencesStrain-Engineered MOSFETsProcess IntegrationMultigate TransistorsDouble-Gate MOSFETO-FinFETTri-Gate FinFETFinFETs Using Gate-Induced StressStress-Engineered FinFETsLayout DependenceSummaryReview QuestionsReferencesNoise in Strain-Engineered Devices, C. MukherjeeNoise MechanismsFundamental Noise Sources1/f Noise in MOSFETsNoise Characterisation in MOSFETsStrain Effects on Noise in MOSFETsNoise in Strain-Engineered MOSFETsNoise in Multigate FETsNoise in Silicon Nanowire Transistors (SNWTs)Noise in Heterojunction Bipolar TransistorsSummaryReview QuestionsReferencesTechnology CAD of Strain-Engineered MOSFETsTCAD CalibrationSimulation of Strain-Engineered MOSFETsDC PerformanceAC PerformanceHybrid Orientation Technology for Strain-Engineered MOSFETsSimulation of Embedded SiGe MOSFETsSummaryReview QuestionsReferencesReliability and Degradation of Strain-Engineered MOSFETsNBTI in Strain-Engineered p-MOSFETsSimulation of NBTI in p-MOSFETsHCI in Strain-Engineered n-MOSFETsSimulation of HCI in n-MOSFETsReliability Issues in FinFETsSummaryReview QuestionsReferencesProcess Compact Modelling of Strain-Engineered MOSFETsProcess VariationPredictive Technology ModellingProcess-Aware Design for ManufacturingProcess Compact ModelProcess-Aware SPICE Parameter ExtractionSummaryReview QuestionsReferencesProcess-Aware Design of Strain-Engineered MOSFETsProcess Design Co-OptimisationClassifications of VariationDesigns for Manufacturing and Yield OptimisationPerformance OptimisationManufacturability OptimisationSummaryReview QuestionsReferencesConclusionsIndex

AUTORE

C K Maiti (Author) , T K Maiti (Indian Institute of Technology, Kharagpur, India Indian Institute of Technology, Kharagpur Indian Institute of Technology, Kharagpur Indian Institute of Technology, Kharagpur Indian Institute of Technology, Kharagpur) (Author)

ALTRE INFORMAZIONI

• Condizione: Nuovo
• ISBN: 9781466500556
• Dimensioni: 9.25 x 6.25 in Ø 1.30 lb
• Formato: Copertina rigida
• Illustration Notes: 191 b/w images, 10 tables and Approx. 148 equations
• Pagine Arabe: 320