Three-Dimensional Integration of Semiconductors Processing, Materials, and Applications

This book starts with background concerning three-dimensional integration - including their low energy consumption and high speed image processing - and then proceeds to how to construct them and which materials to use in particular situations. The book covers numerous applications, including next generation smart phones, driving assistance systems, capsule endoscopes, homing missiles, and many others. The book concludes with recent progress and developments in three dimensional packaging, as well as future prospects.

Chapter 1 - Research and Development History of Three Dimensional (3D) Integration Technology 1.1 Introduction 1.1.1 The International Technology Roadmap for Semiconductors 1.1.2 Three-dimensional Integration Technology 1.2 Motivation for 3D Integration Technology y 1.3 Research and Development History of 3D Integration Technology R&D History of 3D Packaging Technology 1.3.1 3D Packaging Technology 1.3.2 Origin of the TSV Concept 1.3.3 Research and Development History of 3D Technology in Organizations 1.3.3.1 Japan 1.3.3.2 Japanese 3D Integration Technology Research and Development Project (Dream Chip) 1.3.3.3 USA 1.3.3.4 Europe 1.3.3.5 Asia 1.3.3.6 International 1.4 Research and Development History of 3D Integration Technology for Applications 1.4.1 CMOS Image Sensor and MEMS 1.4.2 DRAM 1.4.3 2.5D with Interposer 1.4.4 Others Chapter 2- Recent Research and Development Activities of Three Dimensional (3D) Integration Technology 2.1 Recent Announcement of Research and Development Activities 2.2 Dynamic Random-Access Memory (DRAM) 2.2.1 Through-Silicon Via (TSV) Technology for DRAM 2.2.2 Wide I/O and Wide I/O2 Mobile DRAM 2.3 Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) DRAM 2.3.1 Hybrid Memory Cube (HMC)High Bandwidth Memory (HBM) DRAM 2.3.2 High Bandwidth Memory (HBM) DRAM 2.4 FPGA and 2.5D 2.5 Others 2.6 New Energy and Industrial Technology Development Organization (NEDO) Japan 2.6.1 Next Generation “Smart Device” Project 2.6.2 Background, Purpose and Target of “Smart Device” Project Chapter 3- TSV Processes 3.1 Deep Silicon Etching by Bosch process 3.1.1 Introduction 3.1.2 Basic characteristics of the Bosch process 3.1.3 Bosch Etching Equipment for TSV 3.1.4 Conclusions 3.2 High Rate Silicon-Via Etching and Basics of Sidewall Etch Reaction by Steady-State Etch Process 3.2.1 Introduction 3.2.2 MERIE Process for TSV Application 3.2.2.1 Effect of RF Frequency 3.2.2.2 Effect of Pressure 3.2.2.3 Effect of Oxygen Addition 3.2.3 Investigation of Sidewall Etch Reaction Induced by SF6/O2 Plasma 3.2.3.1 Effect of Oxygen Addition 3.2.3.2 Effect of Temperature 3.2.3.3 Effect of SiF4 Addition 3.2.4 Conclusion 3.3 Low Temperature CVD Technology 3.3.1 Introduction 3.3.2 Cathode-Coupled PECVD (LS-CVD) 3.3.3 Low Temperature SiO2 Deposition 3.3.3.1 Wafer Temperature During Low Temperature Deposition 3.3.3.2 Step Coverage in Si Via Holes 3.3.3.3 Electrical Characteristics of SiO2 Film Deposited at Low Temperature 3.3.3.4 Stress Control of SiO2 Film Deposited Using LS-CVD 3.3.4 Conclusion 3.4 Electrodeposition for Via-Filling 3.4.1 Cu+ Ion as an Accelerant Additive of Copper Electrodeposition 3.4.2 Relation between via Filling and Cu+ Ion by Periodical Reverse Current Waveform 3.4.3 Simulation of Cu+ Ion Distribution inside the Via 3.4.4 High Speed via Filling Electrodeposition by Other Organizations 3.4.5 Reduction of Thermal Expansion Coefficient of Electrodeposited Copper for TSV by Additive Chapter 4 - Wafer Handling and Thinning Processes 4.1 Wafer Thinning Solution for TSV Devices 4.1.1 Introduction 4.1.2 General Thinning 4.1.3 Wafer Thinning for TSV devices 4.1.4 TTV control 4.1.5 Summary 4.2 A Novel Via Middle TSV Thinning Technology by Si/Cu Grinding and CMP 4.2.1 Introduction 4.2.2 Methods 4.2.3 Results and Discussion 4.2.3.1 Si/Cu Same Rate CMP (1st CMP) 4.2.3.2 TSV Protrusion CMP (2nd CMP) 4.2.3.3 Post CMP Cleaning after 2nd CMP 4.2.4 Conclusion 4.3 Temporally Bonding 4.3.1 Background 4.3.2 The 3MTM Temporary Bonding Materials 4.3.3 The 3MTM Temporary Adhesive 4.3.4 Laser Absorbing Layer 4.3.5 The Next Steps 4.4 Temporary Bonding and Debonding for Through-Silicon Via (TSV) Processing 4.4.1 Introduction 4.4.2 Temporary Bonding and Debonding Process 4.4.3 Debonding Method 4.4.4 Functions and Performance Requirements for Temporary Bonding Device 4.4.5 Ability and Performance Requirements for Debonding Devices 4.4.6 Tokyo Electron’s Temporary Bonder and Debonder Device Concept and Lineup 4.4.7 Future Outlook Chapter 5- Wafer and Die Bonding Processes 5.1 Permanent Wafer Bonding 5.1.1 Introduction 5.1.2 Low Temperature or Room Temperature Wafer Direct Bonding Method and Application 5.1.2.1 Fusion Bonding 5.1.2.2 Surface Activated Bonding 5.1.2.3 Anodic Bonding 5.1.2.4 Cu2Cu/Oxide Hybrid bonding 5.1.2.5 Conclusion of Low Temperature or Room Temperature Wafer Direct Bonding Methods and Their Applications 5.1.2.6 Future Outlook for Bonding Application Using Low Temperature or Normal Room Temperature Wafer Direct Bonding Methods 5.1.3 Requests Made to Equipment Makers and Initiatives Regarding Low Temperature or Room Temperature Wafer Direct Bonding Methods 5.1.3.1 Post BAA 5.1.3.2 Scaling 5.1.3.3 Distortion 5.1.3.4 Bonding strength 5.1.3.5 Void 5.1.4 Tokyo Electron Initiatives 5.1.5 Conclusion 5.2 Underfill Materials 5.2.1 Technical Trend for Three Dimensional Integration Packages and Underfill Materials 5.2.2 Requirements for Underfill Materials 5.2.2.1 Requirements for CUF and Material Technology Trend 5.2.2.2 Requirements for NCP and Material Technology Trend 5.2.3 Application to CUF between the Stacked Chips 5.3 Non-Conductive Films 5.3.1 Introduction 5.3.2 Required Material Feature from Bonding Process 5.3.3 Voiding Issue in NC 5.3.4 High Through Put NCF-TCB Chapter 6- Metrology and Inspection 6.1 Principles of Spectroscopic Reflectometry 6.1.1 Introduction 6.1.2 Measurement 6.1.3 Setup 6.1.4 Analysis 6.1.5 Conclusion 6.2 Low Coherence Interferometry for 3D-IC TSV 6.2.1 Optical Measurement of Topographies and Thicknesses 6.2.1.1 3D-IC TSV Needs Tomography 6.2.1.2 Tomography with Low Coherence Interferometry 6.2.2 Theory of Optical Coherence Tomography 6.2.2.1 Basic Principle 6.2.2.2 Time Domain OCT 6.2.2.3 Fourier Domain OCT 6.2.3 Practical Considerations 6.2.4 Conclusion 6.3 Silicon and Glue Thickness Measurement for Grinding 6.3.1 Introduction 6.3.2 TSV Wafer Manufacturing Method and Challenges of Grinding 6.3.3 Features of BGM300 6.3.4 Verifying BGM300 Measurement Results 6.3.5 Measurement after Grinding 6.3.6 Optimized wafer Grinding Based on Via Height Information from BGM300 6.3.7 Conclusion 6.4 3D X-ray Microscopy Technology for Non-Destructive Analysis of Through-Silicon Vias 6.4.1 Introduction 6.4.2 Fundamentals of X-ray Microscopy 6.4.2.1 Physics of X-ray Imaging 6.4.2.2 3D X-ray Microscopy 6.4.3 Applications for TSV Process Development 6.4.4 Applications for TSV Failure Analysis 6.4.5 Summary 6.5 Wafer Warpage and Local Distortion Measurement 6.5.1 Introduction 6.5.2 Basic Functions of WDM300 6.5.3 Measurement and Analysis of Local Deformations 6.5.4 Application 6.5.5 Summary Chapter 7 - TSV Characteristics and Reliability: Impact of 3D Integration Processes on Device Reliability 7.1 Introduction 7.2 Impact of Cu Contamination on Device Reliabilities in Thinned 3D-IC Chip 7.2.1 Impact of Cu Diffusion at Backside Surface in Thinned 3D-IC Chip 7.2.1.1 Effect of Intrinsic Gettering (IG) layer 7.2.1.2 Effect of Extrinsic Gettering (EG) layer 7.2.2 Impact of Cu Diffusion from Cu Via 7.2.2.1 Effect of the Barrier Thickness and the Scallop Roughness 7.2.2.2 Effect of the Annealing Temperature 7.2.2.3 Keep Out Zone (KOZ) Characterization by Cu Diffusion from Cu Via 7.3 Impact of Mechanical Stress/Strain on Device Reliability in Stacked IC 7.3.1 Micro-Bump Induced Local Stress in Stacked IC 7.3.2 Si Mechanical Strength Reduction by Thinning 7.4 Impact of 3D Integration Process on DRAM Retention Characteristics 7.4.1 Impact of Mechanical Strength on Retention Characteristics in Thinn DRAM Chip 7.4.2 Impact of Cu Contamination on Memory Retention Characteristics in DRAM Chip Chapter 8 - Trends in 3D Integrated Circuit (3D-IC) Testing Technology 8.1 Crucial Issues and Key Technologies for 3D-IC Testing 8.2 Research Trends in Pre-bond Test for 3D-IC 8.3 Research Trends in Post-bond Test for 3D-IC 8.4 Research Trends in Automatic Test Pattern Generator (ATPG) and Test Scheduling for TSVs in 3D-IC 8.5 An Accurate Resistance Measuring Method for TSVs

Kazuo Kondo is Professor at Department of Chemical engineering, Osaka Prefecture University. He took his PhD in Chemical Engineering at the University of Illinois in 1981. He has worked for Sumitomo Metal Industries, Hokkaido University and Okayama University. He has 200 research publications and 100 patents. His major research is Copper Electrodeposition for TSV. His research extends in various fields not only in electrodeposition, but also in battery and CVD. He is member of Electrochemical Society, IEEE, Society of Chemical engineering Japan, Japanese Institute of Electronics Packaging, Surface Finishing Society of Japan, Materia Japan, Electrochemistry Japan and Japanese Society of Applied Physics.

 Morihiro Kada is the invited researcher of The National Institute of Advanced Industrial Science and Technology (AIST) and the part-time researcher of Osaka Prefecture University. Prior to joining to AIST and the university he was the consultant of Association of Super-Advanced Electronics Technologies (ASET). Since April 2007 he has been heading the Japanese national R&D project on 3D-Integration technology as the Project in ASET. Before joining to ASET, he had been the General Manager of the Advanced Packaging Development Department in Sharp Corporation. He has more than forty years experience in semiconductor packaging engineering, with major emphasis on developing chip scale, chip stack package and Three Dimensional-System in Package (3D-SiP) as the pioneer of 3D-Integration technology in the world.

Kenji Takahashi is a Chief Specialist at Memory Packaging Development Department, Memory Division, Semiconductor & Strage Company, Toshiba Corporation. He received a M.E. Degree of from Chemical Engineering at the University of Tokyo in 1984 and Ph.D. from Information Science and Electrical Engineering at Kyushu University in 2010. His major research and development is focused on semiconductor packaging and

chip package interaction, especially through-silicon via technology. He was the Research Manager of Electronic System Integration Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET). He is a Senior Member of IEEE, a member of Society for Chemical Engineers, Japan, Institute of Electronics, Information and Communication Engineers and Japanese Institute of Electronics Packaging.