Model And Design Of Improved Current Mode Logic Gates - Gupta Kirti; Pandey Neeta; Gupta Maneesha | Libro Springer 12/2019 - HOEPLI.it


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gupta kirti; pandey neeta; gupta maneesha - model and design of improved current mode logic gates

Model and Design of Improved Current Mode Logic Gates Differential and Single-ended

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Dettagli

Genere:Libro
Lingua: Inglese
Editore:

Springer

Pubblicazione: 12/2019
Edizione: 1st ed. 2020





Sommario

CHAPTER 1        INTRODUCTION

1.1 Background
1.2 Available Literature 
1.2.1 Various CML topologies
1.2.2 Modeling and Design Approaches
1.2.3 System Application
1.3 Organization of the Book

CHAPTER 2        CML GATES: BASIC CONCEPTS

2.1 Introduction
2.2 Basic Concepts
2.3 Differential CML Gates
2.3.1 Operation of the differential CML inverter 
2.3.2 Analysis of the differential CML inverter 
2.3.2.1 Static model
2.3.2.2 Delay model
2.3.3 Design of the differential CML inverter
2.3.4 Realization of the basic gates
2.4 Single-ended CML Gates
2.4.1 Operation of the PFSCL inverter 
2.4.2 Analysis of the PFSCL inverter 
2.4.2.1 Static model
2.4.2.2 Delay model
2.4.3 Design of the PFSCL inverter
2.4.4 Realization of the basic gates
2.5 Concluding Remarks

CHAPTER 3 DIFFERENTIAL CML GATES WITH MODIFIED PDN

3.1 Introduction
3.2 Literature Survey
3.3 New Appraoch
3.4 Improved Combinational Gates with Modified PDN
3.4.1 Operation of the improved XOR gate
3.4.2 Analysis of the improved XOR gate
3.4.2.1 Static model
3.4.2.2 Delay model
3.4.3 Design of the improved XOR gate
3.4.4 Performance comparison
3.4.4.1 High speed design
3.4.4.2 Power efficient design
3.4.4.3 Low power design
3.5 Improved Sequential Gates with Modified PDN 
3.5.1 Operation of the improved D latch
3.5.2 Analysis of the improved D latch 
3.5.2.1 Static model
3.5.2.2 Delay model
3.5.3 Design of the improved D latch
3.5.4 Performance comparison
3.5.4.1 High speed design
3.5.4.2 Power efficient design
3.5.4.3 Low power design
3.6 Concluding Remarks

CHAPTER 4 CML GATES WITH MODIFIED CURRENT SOURCE 

4.1 Introduction
4.2 Survey of the Current Source Modifications
4.3 Dynamic Current Source
4.3.1 Existing NN-dynamic current source
4.3.2 New NP-dynamic current source
4.4 Improved Differential CML Gates with NP-dynamic current source
4.4.1 Operation of the D-MCML-NP inverter
4.4.2 Design of the D-MCML-NP inverter
4.4.3 Power consumption analysis
4.5 Improved PFSCL Gates with NN-dynamic current source
4.5.1 Operation of the D-PFSCL-NN inverter
4.5.2 Design of the D-PFSCL-NN inverter
4.5.3 Power consumption analysis
4.6 Improved PFSCL Gates with NP- dynamic current source
4.6.1 Operation of the D-PFSCL-NP inverter
4.6.2 Design of the D-PFSCL-NP inverter
4.6.3 Power consumption analysis
4.7 Multi-stage Applications
4.7.1 Existing self-timed buffer
4.7.2 Improved self-timed buffer
4.8 Performance Comparison
4.8.1 Performance comparison of the differential D-CML gates
4.8.2 Performance comparison of the D-PFSCL gates
4.9 Concluding Remarks

CHAPTER 5 CML GATES WITH MODIFIED LOAD 

5.1 Introduction
5.2 Available Loads
5.3 New load (NP-Load)
5.3.1 Analysis of the NP-load
5.3.2           Resistance of the NP-load
5.4 Improved Differential CML Gates with Modified Load
5.4.1   Operation of the MCML-CC inverter
5.4.2   Analysis of the MCML-CC inverter
5.4.2.1 Static model
5.4.1.1 Delay model
5.4.3 Design of the MCML-CC inverter
5.4.4 Performance comparison
5.5   Improved PFSCL Gates with Modified Load
5.5.1        Operation of the PFSCL-CC inverter
5.5.2     Analysis of the PFSCL-CC inverter
5.5.2.1 Static model
5.5.2.2 Delay model
5.5.3     Design of the PFSCL-CC inverter
5.5.4     Performance comparison
5.6     Concluding Remarks

CHAPTER 6 PFSCL CIRCUITS WITH REDUCED GATE COUNT 

6.1 Introduction
6.2 Existing Realization of PFSCL circuits
6.3 New Realization of PFSCL circuits
6.3.1 New fundamental cell
6.3.1.1   Architecture and operation
6.3.1.2   Analysis of the fundamental cell 
6.3.2 Improved Realization of the PFSCL circuits
6.3.3 Performance comparison
6.4 Concluding Remarks

CHAPTER 7 TRI-STATE CML CIRCUITS

7.1 Introduction
7.2 Literature Survey on Tri-state CML Circuits
7.2.1 Switch based tri-state CML circuit
7.2.2 Voltage follower based tri-state CML circuit
7.3 Improved Differential Tri-state CML circuit 
7.3.1 Operation of the circuit
7.3.2 Performance comparison
7.3.3 Application examples
7.4 Concluding Remarks

REFERENCES





Trama

This book presents MOSFET-based current mode logic (CML) topologies, which increase the speed, and lower the transistor count, supply voltage and power consumption. The improved topologies modify the conventional PDN, load, and the current source sections of the basic CML gates.

Electronic system implementation involves embedding digital and analog circuits on a single die shifting towards mixed-mode circuit design. The high-resolution, low-power and low-voltage analog circuits are combined with high-frequency complex digital circuits, and the conventional static CMOS logic generates large current spikes during the switching (also referred to as digital switching noise), which degrade the resolution of the sensitive analog circuits via supply line and substrate coupling. This problem is exacerbated further with scaling down of CMOS technology due to higher integration levels and operating frequencies. In the literature, several methods are described to reduce the propagation of the digital switching noise. However, in high-resolution applications, these methods are not sufficient. The conventional CMOS static logic is no longer an effective solution, and therefore an alternative with reduced current spikes or that draws a constant supply current must be selected. The current mode logic (CML) topology, with its unique property of requiring constant supply current, is a promising alternative to the conventional CMOS static logic.





Autore

Dr. Kirti Gupta received B.Tech. in Electronics and Communication Engineering from Indira Gandhi Institute of Technology, Delhi in 2002, M. Tech. in Information Technology from School of Information Technology in 2006. She received her Ph.D. in Electronics and Communication Engineering from Delhi Technological University, in 2016. Since 2002, she is with Bharati Vidyapeeth’s College of Engineering, New Delhi and is presently serving as Professor in the same institute. A life member of ISTE, and senior member of IEEE, she has published more than 100 research papers in international, national journals and conferences. Her teaching and research interest is in digital VLSI design.

Dr. Neeta Pandey received her M.E. in Microelectronics from Birla Institute of Technology and Sciences, Pilani in 1991 and Ph.D. from Guru Gobind Singh Indraprastha University, Delhi in 2009. She has served in Central Electronics Engineering Research Institute, Pilani, Indian Institute of Technology, Delhi, Priyadarshini College of Computer Science, Noida and Bharati Vidyapeeth’s College of Engineering, Delhi in various capacities. At present, she is a professor in the ECE department, Delhi Technological University. Her teaching and research interests include analog and digital VLSI design.

A life member of ISTE, and senior member of IEEE, USA, she has coauthored over 100 papers in international, national journals of repute and conferences. 

Dr. Maneesha Gupta is currently a Professor at the Electronics & Communication Engineering Department of the Netaji Subhas University of Technology, India. She received her B.E. in Electronics & Communication Engineering from the Government Engineering College, Jabalpur in 1981, M.E. in Electronics & Communication Engineering from the same university in 1983, and her PhD. in Electronics Engineering (Analysis, Synthesis & Applications of Switched Capacitor Circuits) from the Indian Institute of Technology, Delhi in 1990.

Her teaching and research interests include switched capacitor circuits and analog signal processing. Dr. Gupta has co-authored over 150 research papers in the above areas in various international/national journals and conferences. 








Altre Informazioni

ISBN:

9789811509810

Condizione: Nuovo
Dimensioni: 235 x 155 mm Ø 453 gr
Formato: Copertina rigida
Illustration Notes:98 Illustrations, black and white
Pagine Arabe: 171
Pagine Romane: xiv






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